DeepInfer hardware: SM100 & Ascend 950 today

Support matrix, benchmark topology, community RFCs for unsupported SKUs, and serving gaps — all linked to upstream. Prefill and Decode are two phases of the same engine.

Today support matrix

From the official README only. If your SKU is not listed, do not force a build.

AcceleratorVendorToolchainEnvStatus
SM100 GPUsNVIDIACUDA 13DEEPINFER_ACCELERATOR=nvidiaSupported
Ascend 950 NPUsHuaweiCANN 9.2DEEPINFER_ACCELERATOR=ascendSupported
Ascend 910C / A3HuaweiCANN 9.1 (proposed)—Draft RFC only · #46
SM90 / H20-3ENVIDIA——Draft RFC only · #47

Benchmark topology (same engine)

README performance charts: measured on 4× SM100 for prefill and 64× SM100 for decode — each within one scale-up domain. Reproduce via examples/sweep/run_sweep.sh. Prefill ≠ a separate product.

PhaseTopology (README)What it measures
Prefill4× SM100 · one scale-up domainNon-cached input throughput vs latency
Decode64× SM100 · one scale-up domainOutput throughput vs per-user speed

Community RFCs — unsupported today

Draft RFCs only. Do not claim 910C, SM90, or H20 are supported. Implementation has not landed; track the PRs.
RFCTargetScope / blockers (from PR text)Link
#46 Ascend 910C / A3 Offline-first single-server; V4.1-Flash W8A8 on CANN 9.1; online serving as a later phase. Documented today remains 950 + CANN 9.2. PR #46
#47 SM90 · 4× H20-3E (141 GB) Native FP4 checkpoint capacity ~499 GB of 564 GB; needs dequant-fused FP8 grouped GEMM (no FP4 tensor core on SM90); Hopper attention — FlashMLA dropped Hopper on 2026.09.30. PR #47

Serving gaps (OSS release)

README lists what a complete inference service still needs — not included in this open-source release:

MissingWhy it matters
KV cache systemOnline multi-turn / high-QPS reuse
VE / Prefill / Decode disaggregationMost engine functionality exists; full service glue is not released
DP load balancingReplica balancing for both prefill and decode

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